This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including high-level programming tools targeting FPGA architectures. This effort is contrasted with other IP reuse efforts. The paper reviews the current approach used by several high-level language compilers to integrate IP within their tool. The CoreLib approach for standardizing this IP integration is proposed followed by an example that demonstrates its utility. Finally, the current state of the effort and future plans are presented. © 2008 Elsevier B.V. All rights reserved.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computer Networks and Communications
- Computer Graphics and Computer-Aided Design
- Artificial Intelligence
Wirthlin, M., Poznanovic, D., Sundararajan, P., Coppola, A., Pellerin, D., Najjar, W., ... Kuzmanov, G. (2008). OpenFPGA CoreLib core library interoperability effort. Parallel Computing, 34(4-5), 231 - 244. https://doi.org/10.1016/j.parco.2008.03.004